PCI Express Gen4 and Gen5 support
The QNX PCIe subsystem supports operation at PCI Express Gen4 (16.0 GT/s per lane) and Gen5 (32.0 GT/s per lane) link speeds, in addition to legacy Gen1–Gen3 speeds.
PCI Express Gen4 and Gen5 support covers the following areas:
- Capability detection — identifying controllers and devices that are capable of Gen4 or Gen5 operation.
- Link configuration — configuring link parameters and initiating link training to bring the link up at the highest commonly supported speed.
- Backward compatibility (fallback) — falling back to a lower generation when high-speed negotiation fails or is unsupported by the link partner.
- Link state reporting — reporting the negotiated link generation, speed, and status to upper-layer (client) software.
Application impact
No application changes are required to take advantage of Gen4 or Gen5 link speeds. The negotiated speed is established automatically during device enumeration and PCIe link training.
Applications that need to query the negotiated link speed or read high-speed diagnostic
registers can do so through the libpci API; refer to the API Reference
for more information on this library.
PCIe extended capability modules
Support for Gen4 and Gen5 functionality is provided through the following PCIe extended capability modules:
| Module | Extended Capability ID | Registers decoded | Used by |
|---|---|---|---|
| pcie_xcap-0x0019.so | 0x0019 – Secondary PCI Express Extended Capability |
|
Gen4, Gen5 |
| pcie_xcap-0x0026.so | 0x0026 – Physical layer 16.0 GT/s Extended Capability |
16.0 GT/s status register | Gen4, Gen5 |
| pcie_xcap-0x0027.so | 0x0027 – Lane margining at the receiver Extended
Capability |
|
Gen4, Gen5 |
| pcie_xcap-0x002A.so | 0x002A – Physical layer 32.0 GT/s Extended Capability |
32.0 GT/s status register | Gen5 only |
For more information on capability modules, refer to the Capability modules
section.